Rack Architecture
Apple's UltraFusion interconnect provides direct die-to-die bandwidth with ultra-low latency, eliminating PCIe bottlenecking across multi-Ultra nodes.
Chassis Cross-Section & Fabric Visualizer
Interactive die topology with live interconnect data streams
Active Simulation
Apple Ultra Silicon (SoC)
UltraFusion Bus (2.5 TB/s)
Unified Memory Channels
Thermal Cold Plate
4 Server Blades • 8 Total M4 Ultra Processors • 4096 GB Pool
Performance Telemetry
NOMINAL
Memory Bandwidth
1638.4
TB/s
Consolidated pool across all Ultra dies
Token Generation Speed
420.5
tok/s
Continuous batching @ 70B FP16 weights
Cluster Efficiency
94.2
%
Interconnect scaling & memory saturation
Total Power Envelope
1850
Watts
At 100% continuous inference compute
Thermal Equilibrium
Optimal Liquid Cooling
Chassis delta T: +14.2°C over ambient