Huawei Ascend vs Nvidia Supercluster Scale Simulator

Deployment Specs Live Modeler

Architecture Preset

Target Accelerator Count 160,000

Primary Accelerator Model

Per-Accelerator TDP (Watts) 600 W

Data Center Facility PUE 1.25

Interconnect Topology & Fabric

Optical Port Speed 400 Gbps

Aggregate Compute

160,000 PFLOPS

FP8 Dense Floating Point

Facility Total Power

120.0 MW

Total Load (with 1.25 PUE)

Bisection Bandwidth

64,000 Tbps

Core Spine Fabric

Cluster Efficiency

74.2%

All-Reduce Scaling Factor

Cluster Fabric Topology: Spines, Pods & Aggregation Layer 5,000 Pods (32 Nodes/Pod)

L3 Super-Spines: 128 Switches | L2 Spine Pods: 512 Switches | Leaf/TOR Racks: 5,000

Huawei Supercluster Plan Current Selection

Physical Accelerator Count 160,000

Theoretical FP8 Compute 160,000 PFLOPS

Direct Server TDP Draw 96.0 MW

Data Center Grid Load (PUE) 120.0 MW

Interconnect Fabric RoCE v2 (400G)

Effective Training Scaling 74.2%

Nvidia H100 Equivalent Footprint Normalized Parity

H100 SXM5 Units Needed 104,500

Theoretical Compute 206,910 PFLOPS

Direct Server TDP Draw 73.2 MW

Data Center Grid Load 91.4 MW

Interconnect Fabric InfiniBand Quantum-2

Effective Training Scaling 86.5%

Supercluster Architecture & Sovereignty Trade-offs

Bloomberg reported that Chinese AI company DeepSeek intends to deploy 160,000 Huawei AI accelerators (believed to center on the Ascend 910C series) in a mega-facility. This project represents China's most audacious bid to reach compute parity with Western hyperscalers without access to TSMC advanced packaging or Nvidia's leading-edge silicon.

Power Density & Substation Demands: At 600W TDP per chip with 160k accelerators, pure compute power draw equals 96 MW. Factoring standard liquid-and-chilled data center PUE (1.25), the total substation demand touches 120.0 MW—equivalent to powering a city of ~100,000 homes.

Interconnect & All-Reduce Bottlenecks: Because Huawei cannot access Nvidia's proprietary NVLink cross-chassis switches, it utilizes advanced multi-rail RoCE v2 Ethernet fabrics. At 160k scale, collective communication (AllGather / ReduceScatter) introduces substantial jitter, pulling effective cluster scaling efficiency down to ~74.2% relative to InfiniBand's ~86.5%.

Blackwell vs Sovereign Clusters: Matching 160k Ascend 910C chips requires approximately 104,500 Nvidia H100 SXM5s or roughly 35,500 Nvidia B200 accelerators, illustrating the footprint and thermal delta between leading-edge 4nm packaging and domestic domestic silicon.

Trace cluster power, efficiency assumptions and bandwidth convention

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This saved cluster planner assigns hypothetical hardware profiles; this explainer does not verify current product specifications or company plans. At one hundred sixty thousand chips and six hundred watts per chip, direct chip power is ninety-six megawatts. Multiplying by the source one point two five power usage effectiveness gives one hundred twenty megawatts facility power. Both bars use four pixels per megawatt. Other server components are not separately added by this calculation, despite its server-power label. The source assigns one petaflop per second FP8 to its default chip profile. One hundred sixty thousand chips therefore sum to one hundred sixty thousand petaflops per second. Its default fabric efficiency starts at seventy-six point five percent and loses two point three percentage points from the logarithmic scale penalty, giving seventy-four point two. Effective compute is then one hundred eighteen thousand seven hundred twenty petaflops per second. Both bars use point zero zero three pixels per petaflop per second. These are source arithmetic assumptions, not measured training throughput. The source bandwidth field multiplies chip count by link speed and divides by one thousand. At one hundred sixty thousand chips and four hundred gigabits per second this gives sixty-four thousand terabits per second. Selecting oversubscribed fabric halves it to thirty-two thousand. Both bars use point zero zero seven pixels per terabit per second. The source calls this bisection bandwidth, but its non-oversubscribed formula does not apply the half-cut factor described in its comment. The topology illustration always draws twenty pod symbols, not all five thousand calculated pods.