Hardware Configuration
8 x 8
100 MHz
Capstone Feasibility Index
High Feasibility (92/100)
Suitable for two-semester Senior Project. RTL systolic array synthesizes cleanly into DSP48E slices with low timing closure risk.
RTL Dataflow & Streaming Pipeline Animation
RUNNING @ 100 MHz
DSP48E Slices
32 / 80
BRAM Blocks
28 / 120
Throughput
84.7 FPS
11.8 ms
Intensity
14.2
OPs / Byte
Thermal Power
1.85 W
Active Dissipation
Roofline Operational Intensity
Operating Point: Compute-Bound (Saturating DSP MAC capability).
Graduation Project Milestone Roadmap
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W1-W4
Quantization & Golden Model: PyTorch/TensorFlow quant training and C++ software emulator golden vectors.
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W5-W8
Line-Buffer & PE RTL: Verilog / VHDL dual-port BRAM sliding window & MAC systolic interconnect.
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W9-W12
AXI DMA & Driver: Vivado Block Design, AXI4-Stream DMA integration, and Linux PYNQ MMIO driver.
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W13-W16
Verification & Defense: Real-time camera feed benchmarking, power validation, thesis writeup.