The Surface-Code Lattice, Live
Blue spheres are data qubits, orange octahedra are measurement (syndrome) qubits. Drag to rotate. Increase code distance d and watch the qubit bill grow while the logical error rate collapses.
Worked Example: the error-correction bargain
The standard rule-of-thumb for surface codes: P_logical ≈ 0.1 × (p / p_th)^((d+1)/2) where p is the physical error rate, p_th ≈ 1% is the threshold, and d is code distance.
Take hardware with p = 0.3% (a good superconducting qubit today) and d = 11. Then (0.3/1)^6 ≈ 7.3 × 10⁻⁴, so P_logical ≈ 7 × 10⁻⁵ per cycle — thousands of times better than the raw qubit.
The price: a distance-11 surface code uses about 2d² − 1 = 241 physical qubits for ONE logical qubit. A machine running Shor's algorithm on RSA-2048 is estimated to need ~few thousand logical qubits — meaning millions of physical qubits. That gap, not qubit count alone, defines the engineering roadmap.
Crucially, error correction only helps if p < p_th. Above threshold, adding qubits makes things worse — try pushing the error slider past 1% in the simulator.
What "Commercially Viable" Actually Requires
Architecture, not arithmetic
Qubits must be wired so syndrome measurements happen every microsecond across the whole chip without crosstalk. Layout, coupling topology and modularity decide whether a design can scale past a demo.
Fabrication yield
Millions of physical qubits means chip fabrication with semiconductor-grade consistency. A 1-in-1,000 defective qubit rate that is fine at 100 qubits becomes thousands of dead qubits at scale.
Cryogenics and control
Superconducting and annealing systems run near 10–15 millikelvin. Every qubit needs control lines; naive wiring melts the fridge budget. Cryo-CMOS controllers and multiplexing are active research fronts.
Real-time decoding
Syndrome data streams out faster than a gigabit per second per logical qubit. Classical decoders must keep up in real time, or the backlog destroys the correction advantage.
Error rates below threshold
All of it is moot unless physical gates beat ~99% fidelity with margin. Improving coherence times and gate calibration multiplies the value of every other advance.
A workload that pays
Commercial viability means some computation — optimization, materials simulation, sampling — delivered cheaper or better than classical rivals. Hardware roadmaps and application roadmaps must converge.