Capacity comes first.
Weights-only capacity is parameter count multiplied by quantized precision. At 500B and 2-bit weights, that is 125 GB before runtime state.
GB = params × bits ÷ 8
A transparent future-hardware stress test
Can a phone push 500B at 50 TPS?
Turn the iPhone 20 NPU-plus-ASIC prediction into constraints you can inspect: weights, memory traffic, and dense compute.
NPU / SYSTOLIC
INFERENCE ASIC
Put the prediction through the math.
The source values are loaded by default. Change assumptions to explore a future Apple design or a hypothetical Chinese-company design. No future benchmark is implied.
MODEL INFERENCE PIPELINESOURCE SCENARIO
Weights125 GB
Memory fabric6.25 TB/s
Compute fabric50 PFLOP/s
Weights only125.00 GB
Min. stream6.25 TB/s
Dense compute50.00 PFLOP/s
Bandwidth gap: 7.72x
Compute gap: 41.67x
Neither constraint clears. This simplified dense baseline needs 7.72x the effective declared bandwidth and 41.67x the declared compute.
The lower-bound arithmetic.
These formulas are deliberately inspectable. Real inference adds KV cache, activations, runtime overhead, and memory movement, while sparsity, MoE routing, caching, and speculative decoding can reduce work.
Every token moves weight.
The optimistic stream bound assumes one full weight pass per generated token and perfect reuse beyond that pass.
TB/s = GB × TPS ÷ 1000
Dense work is severe.
The common dense-decoder estimate is roughly two operations per active parameter per generated token.
PFLOP/s = 2 × params × TPS ÷ 1000
Who wins is still unknown.
Architecture names do not decide a benchmark. Memory packaging, thermal limits, power, software, active parameter count, and silicon utilization decide what survives outside a slide.
Source baseline
Exactly 500B parameters and 50 TPS. This is the post's prediction translated into a measurable constraint set.
Apple scenario
A labeled assumption set, not a leaked iPhone specification. Adjust its bandwidth and compute to discover the break-even point.
China scenario
A parallel hypothetical, not a composite benchmark for Chinese companies. The same formulas keep the comparison honest.
50 TPS is an outcome. The chip diagram is only the beginning of the explanation.
Keep the assumptions with the answer.
Export the current scenario, formulas, gaps, and caveats as a durable hardware brief.