Foundry Output Telemetry
MODEL: INTEL-US-FAB-v2.6
Effective Yield Rate
91.4%
Ramped node blend
Unit Cost Delta
+14.2%
vs overseas pure fab
Geopolitical Risk Score
22.5
Lower is safer (0-100)
Time to Volume Market
18 mos
Full packaging ramp
Volume Sensitivity & Risk Trade-off
Yield Rate (%)
Unit Cost Delta (%)
Risk Score
Supply Chain Stage Bottleneck Analysis
1. Wafer Fabrication
92% CAP
Intel Ohio/Arizona fabs allocating EUV lines for high-density Apple memory substrate.
2. Advanced Packaging
BOTTLENECK
Foveros / 2.5D substrate capacity ramp critical; currently limiting immediate sub-12mo rollout.
3. Final Sub-Assembly
STABLE
North American test & assembly facilities operational with lower transit friction.
Executive Sourcing Verdict
Proceed with dual-sourcing model leveraging Intel U.S. nodes for domestic resilience.