ZK

R1CS Circuit Formal Verifier

🌐 R1CS Dependency Graph View (Cytoscape.js)
8 Elements (5 Signals, 3 Gates)
Witness Signal
Multiplier Gate
Constraint Target
🧮 Matrix Inspector ($A w \circ B w = C w$)

Sparse Coefficient Matrices ($A, B, C$) evaluated against Witness Vector $w = [w_0, w_1, w_2, w_3, w_4]$.

Gate / Constraint $A \cdot w$ $B \cdot w$ $C \cdot w$ Sat?
Witness Vector Inputs ($w$):
⚠️ WARNING: UNDER-CONSTRAINED SIGNALS DETECTED
Signal w4 has remaining degree-of-freedom. Multiple valid witness extensions exist for the same input!
UNSOUND (Degree = 1)
🚀 Multi-Node GPUDirect RDMA Prover Engine Simulator
Scale Range: $2^{16}$ to $2^{28}$ Constraints
Effective RDMA Throughput
384.2 Gbps
GPUDirect All-Reduce Bus
Proof Convergence Time
1420 ms
Geometric MSNARK Convergence
Matrix Sparse Rank
4
Active Constraint Dim
Constraint Space
268.4M
$2^{28}$ Total Field Ops

Formal Verification Summary: STARK-over-SNARK Recursion Gate (v2.0 Under-Constraint Test)

Verification status calculated live. All checks completed.

Formal Verification Status
SATISFIED_UNSOUND
Unconstrained Signals
[w4]
Witness Evaluation
100% SATISFIED
Estimated Prover Time ($2^{28}$)
1420 ms @ 64 NDR
Verification Evidence JSON Artifact:
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