300mm Silicon Wafer Layout & Defect Map
💡 Gesture Controls: Drag corners of the die highlight overlay on the wafer to resize area interactively.
Good Dies: 412 | Defects: 85
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Dynamic Power-Delay Trade-off & Chiplet Split Analysis
Loading microarchitectural power dynamic curve...
Murphy Yield Equation: Y = [(1 - e^(-D * A)) / (D * A)]² | Poisson: Y = e^(-D * A)
Workload Sector Presets
Fabrication & Process Geometry
Process Node
5 nm FinFET
3nm GAA5nm7nm28nm180nm
Die Area (A)
120 mm²
Defect Density (D)
0.12 / cm²
Wafer Diameter
300 mm
Multi-Chiplet Split (2x Dies)
Silicon Yield & Thermal Telemetry
Estimated Yield
86.4%
Murphy Model
Good Dies / Wafer
412
out of 477 total
Cost / Good Die
$42.80
Wafer: $17,630
Freq / Thermal Cap
3.85 GHz
Heat Density: 48 W/cm²
PROCESSED WORKLOAD: AI ACCELERATOR | GOOD DIES: 412