Benchmark Leak Detector

Evaluate rumored processor benchmark submissions for statistical plausibility. Audit IPC leaps, multi-core scaling efficiency, cryptographic subtest spikes, and motherboard identifier anomalies before citing online leaks.

Load leak profile:

Submission Parameters

Hardware Target & Clocks Processor / Chip Label

Reported Clock (GHz) Baseline Gen Clock Preceding Gen baseline

Performance Cores (P) Efficiency Cores (E)

Geekbench 6 Scores

Single-Core Score Baseline Gen Single-Core

Multi-Core Score Baseline Gen Multi-Core

Subtest Score Distribution Integer Subscore Ratio 1.05x Relative to ST baseline trend Floating Point & Matrix Ratio 1.12x Crypto / AES Subscore Ratio 2.45x Excessive spike (>1.8x) flags synthetic patching

Metadata & Header Validation Motherboard / Board Identifier e.g. Mac16,1, J614c, or AlderLake

OS Build String Compiler Flag

Pure IPC Uplift

+13.8%

Normal Clock-normalized

Multi-Core Efficiency

104.2%

Impossible (>100%)

Crypto Anomaly

2.45x

Fake Spike

Metadata Integrity

Fail

Invalid Board ID

Architectural Scaling Radar Normalized vs Theoretical Max

Theoretical vs Reported Scaling P-Core Saturation Threshold

Forensic Findings & Red Flags 3 Red Flags Detected

Audit complete: 3 critical flags detected in benchmark payload.

How Leaked Benchmarks Are Fabricated

Online database entries for unreleased hardware (such as Apple M-series, Intel Core Ultra, and AMD Ryzen processors) are routinely spoofed on platforms like Geekbench Browser through:

Hackintosh / OpenCore Plist Spoofing: Modifying the system-id, board-id, and SMBIOS processor string while running an existing overclocked chip.
Instruction Set Overclocking: Injecting pre-computed AES/SHA acceleration hashes into the Primate Labs cryptographic subtest, inflating single-thread scores by 200–300%.
Thermal Saturated Linear Multipliers: Scripting fake JSON benchmark bundles with perfect linear scaling (e.g. 10 P-cores giving exactly 10x single-core performance), which is physically impossible due to interconnect and memory bus bottlenecks.

Physical Rules of Semiconductor Scaling

Legitimate generation-over-generation architectural improvements obey tight silicon physics:

IPC Limits: An architectural node shrink (e.g., TSMC N3E to N2) typically yields 6% to 16% IPC uplift. Any claimed leap above 25% on standard pipelines requires radical architectural paradigm shifts.
Amdahl's Law in Multi-Core: Even with 100% thread availability, synchronization overhead, L3 cache contention, and power throttling prevent multi-core scaling efficiency from exceeding 85% to 92% of pure P-core theoretical sum.
Firmware Board IDs: Apple internal silicon engineering samples use specific alphanumeric codenames (e.g. Mac15,x, T8132, J514). Invented patterns like Mac17,2-FAKE instantly fail checksum verification.