Microarchitectural Clock
Cycle 38 / 60
Transient Window Width
24 Cycles (14-38)
Cache Hierarchy Footprint
Line #115 (MOD 16: #3) CACHED
Attacker Leak Confidence
99.8% (Hit Latency 4c)
CPU Instruction Pipeline & Reorder Buffer (ROB) Execution Timeline
X-Axis: Clock Cycles | Blue: Arch | Orange: Transient | Red: Squash
Transient Race Mechanism: Instruction
I2 loads forbidden secret memory during the branch mispredict penalty window. Although the CPU registers roll back at cycle 38 when I0 squash fires, the victim array line probe_array[secret * 64] remains warmed inside the L1/L3 cache tag state.
Attacker Timing Probe (Flush+Reload) Latency Distribution
Threshold: < 50 cycles = Cache Hit (Leaked)
L1 Data Cache Tag Array (16 Sets / 64B lines)
L1 HIT DETECTED
Line 0x00
■ Active Side-Channel Hot Line
Line 0x0F
Attacker Leaked Byte Recovery
MOD 16 INDEX
Architectural Target Secret
0x73 ('s')
➔
Side-Channel Recovered Byte
0x73 ('s')
Signal-to-Noise Ratio: 18.4 dB | False Positives: 0.002%
Microarchitectural Trace Log
INSPECTION LOG